Hardware Implementation of the Rössler Chaotic System for Securing Chaotic Communication

In this paper, a real-time implementation of the Rössler chaotic system in a Field Programmable Gate Array (FPGA) is presented. At first, we use directly the VHDL language for the hardware description of the system, contrary to some previous works where the Xilinx system generator of MATLAB/SIMULINK is used to generate the VHDL code. Then, after a step of optimization, to reduce the resources of the circuit target Virtex-II xcv1000-4fg456, we implement the chaotic system on FPGA. The real-time chaotic signals obtained at the output of the FPGA are then compared with those obtained by MATLAB and ModelSim simulation, in order to validate our results. However, the goal of this work is to introduce this chaotic system in an eventual secure digital chaotic communication system.